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 TC7129
4-1/2 Digit Analog-to-Digital Converters with On-Chip LCD Drivers
Features
* * * * * * * * * Count Resolution: 19,999 Resolution on 200mV Scale: 10V True Differential Input and Reference Low Power Consumption: 500A at 9V Direct LCD Driver for 4-1/2 Digits, Decimal Points, Low Battery Indicator, and Continuity Indicator Over Range and Under Range Outputs Range Select Input: 10:1 High Common Mode Rejection Ratio: 110dB External Phase Compensation Not Required
General Description
The TC7129 is a 4-1/2 digit analog-to-digital converter (ADC) that directly drives a multiplexed liquid crystal display (LCD). Fabricated in high performance, low power CMOS, the TC7129 ADC is designed specifically for high resolution, battery powered digital multimeter applications. The traditional dual slope method of A/D conversion has been enhanced with a successive integration technique to produce readings accurate to better than 0.005% of full scale, and resolution down to 10V per count. The TC7129 includes features important to multimeter applications. It detects and indicates low battery condition. A continuity output drives an annunciator on the display, and can be used with an external driver to sound an audible alarm. Over range and under range outputs and a range change input provide the ability to create auto-ranging instruments. For snapshot readings, the TC7129 includes a latch-and-hold input to freeze the present reading. This combination of features makes the TC7129 the ideal choice for full featured multimeter and digital measurement applications.
Applications
* Full Featured Multimeters * Digital Measurement Devices
Device Selection Table
Package Code TC7129CPL TC7129CKW TC7129CLW Pin Layout Normal Formed - Package 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC Temperature Range 0C to +70C 0C to +70C 0C to +70C
Typical Application
Low Battery Continuity V+ 5pF
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
TC7129
120kHz
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
330k
*
0.1F 1F 150k
+ +
0.1 F
10pF 20 k 0.1F V+
10k 9V
-
100k
+ *Note: RC network between Pins 26 and 28 is not required.
VIN
2002 Microchip Technology Inc.
DS21459B-page 1
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TC7129
Package Type
40-Pin PDIP
OSC1 OSC3 ANNUNICATOR B1, C1, CONT A1, G1, D1 F1, E1, DP1 B2, C2, LO BATT A2, G2, D2 F2, E2, DP2 1 2 3 4 5 6 7 8 9 40 OSC2 39 DP1 38 DP2 37 RANGE 36 DGND 35 REF LO 34 REF HI 33 IN HI 32 IN LO
B3, C3, MINUS 10 Display Output Lines A3, G3, D3 11 F3, E3, DP3 12 B4, C4, BC5 13 A4, G4, D4 14 F4, E4, DP4 15 BP3 16 BP2 17 BP1 18 VDISP 19 DP4/OR 20
TC7129CPL
31 BUFF 30 CREF29 CREF+ 28 COMMON 27 CONTINUITY 26 INT OUT 25 INT IN 24 V+ 23 V22 LATCH/HOLD 21 DP3/UR
ANNUNCIATOR
B1, C1, CONT
A1, G1, D1
B1, C1, CONT
44-Pin QFP
A1, G1, D1
ANNUNCIATOR
44-Pin PLCC
RANGE
RANGE
DGND
OSC3
OSC1
OSC2
DP1
DP2
NC
44 43 42 41 40 39 38 37 36 35 34 F1, E1, DP1 1 B2, C2, BATT 2 A2, G2, D2 3 F2, E2, DP2 4 B3, C3, MINUS 5 NC 6 A3, G3, D3 7 F3, E3, DP3 8 B4, C4, BC5 9 A4, G4, D4 10 F4, E4, DP4 11 12 13 14 15 16 17 18 19 20 21 22
DP4/OR DP3/UR LATCH/HOLD VDISP INT IN NC BP3 BP2 BP1 V+ V-
6 33 REF LO 32 REF HI 31 IN HI 30 IN LO 29 BUFF F1, E1, DP1 7 B2, C2, BATT A2, G2, D2 8 9
5
4
3
2
1
44 43 42 41 40 39 REF LO 38 REF HI 37 IN HI 36 IN LO 35 BUFF
F2, E2, DP2 10 B3, C3, MINUS 11 NC 12 A3, G3, D3 13 F3, E3, DP3 14 B4, C4, BC5 15 A4, G4, D4 16 F4, E4, DP4 17 18 19 20 21 22 23 24 25 26 27 28
DP4/OR DP3/UR VDISP LATCH/HOLD INT IN NC BP1 BP3 BP2 V+ V-
DGND
OSC3
OSC1
OSC2
DP1
DP2
NC
TC7129CKW
28 NC 27 CREF26 CREF+ 25 COMMON 24 CONTINUITY 23 INT OUT
TC7129CLW
34 NC 33 CREF32 CREF+ 31 COMMON 30 CONTINUITY 29 INT OUT
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DS21459B-page 2
2002 Microchip Technology Inc.
TC7129
1.0 ELECTRICAL CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings*
Supply Voltage (V+ to V-)....................................... 15V Reference Voltage (REF HI or REF LO) ......... V+ to VInput Voltage (IN HI or IN LO) (Note 1)........... V+ to VVDISP .......................................... V+ to (DGND - 0.3V) Digital Input (Pins 1, 2, 19, 20, 21, 22, 27, 37, 39, 40) .......................... DGND to V+ Analog Input (Pins 25, 29, 30) ........................ V+ to VPackage Power Dissipation (TA 70C) Plastic DIP ..................................................... 1.23W PLCC ............................................................. 1.23W Plastic QFP .................................................... 1.00W Operating Temperature Range ............... 0C to +70C Storage Temperature Range .............. -65C to +150C
TC7129 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: V+ to V- = 9V, VREF = 1V, TA = +25C, fCLK = 120kHz, unless otherwise indicated. Pin numbers refer to 40-pin DIP. Symbol Input Zero Input Reading Zero Reading Drift Ratiometric Reading Range Change Accuracy RE NL CMRR CMVR eN IIN Rollover Error Linearity Error Common Mode Rejection Ratio Common Mode Voltage Range Noise (Peak-to-Peak Value not Exceeded 95% of Time) Input Leakage Current Scale Factor Temperature Coefficient Power VCOM Common Voltage Common Sink Current Common Source Current DGND Digital Ground Voltage Sink Current Supply Voltage Range IS Supply Current Excluding Common Current 2.8 -- -- 4.5 -- 6 -- 3.2 0.6 10 5.3 1.2 9 0.8 3.5 -- -- 5.8 -- 12 1.3 V mA A V mA V mA V+ to Pin 28 Common = +0.1V Common = -0.1V V+ to Pin 36, V+ to V- = 9V DGND = +0.5V V+ to VV+ to V- = 9V -0000 -- 9997 0.9999 -- -- -- -- -- -- -- -- 0000 0.5 9999 1.0000 1 1 110 (V-) + 1.5 (V+) - 1 14 1 2 +0000 -- 10000 1.0001 2 -- -- -- -- -- 10 7 Counts V/C Counts Ratio Counts Counts dB V V VP-P pA ppm/C VIN = 0V, 200mV Scale VIN = 0V, 0C < TA < +70C VIN = VREF = 1000mV, Range = 2V VIN = 1V on High Range, VIN = 0.1V on Low Range VIN- = VIN+ = 199mV 200mV Scale VCM = 1V, VIN = 0V, 200mV Scale VIN = 0V 200mV Scale VIN = 0V 200mV Scale VIN = 0V, Pins 32, 33 VIN = 199mV, 0C < TA < +70C External VREF = 0ppm/C Parameter Min Typ Max Unit Test Conditions
Note 1: Input voltages may exceed supply voltages, provided input current is limited to 400A. Currents above this value may result in invalid display readings, but will not destroy the device if limited to 1mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
2002 Microchip Technology Inc.
DS21459B-page 3
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TC7129
TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: V+ to V- = 9V, VREF = 1V, TA = +25C, fCLK = 120kHz, unless otherwise indicated. Pin numbers refer to 40-pin DIP. Symbol fCLK Parameter Clock Frequency VDISP Resistance Low Battery Flag Activation Voltage Digital Continuity Comparator Threshold Voltages Pull-down Current "Weak Output" Current Sink/Source Pin 22 Source Current Pin 22 Sink Current 100 -- -- -- -- -- -- 200 200 2 3/3 3/9 40 3 -- 400 10 -- -- -- -- mV mV A A A A A VOUT Pin 27 = High VOUT Pin 27 = Low Pins 37, 38, 39 Pins 20, 21 Sink/Source Pin 27 Sink/Source Min -- -- 6.3 Typ 120 50 7.2 Max 360 -- 7.7 Unit kHz k V VDISP to V+ V+ to VTest Conditions
Note 1: Input voltages may exceed supply voltages, provided input current is limited to 400A. Currents above this value may result in invalid display readings, but will not destroy the device if limited to 1mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
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DS21459B-page 4
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TC7129
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Symbol OSC1 OSC3 B1, C 1, CONT A1, G1, D1 F1, E1, DP1 A2, G2, D2 F2, E2, DP2 B3, C3, MINUS A3, G3, D3 F3, E3, DP3 B4, C4, BC5 A4, D 4, G4 F4, E4, DP4 BP3 BP2 BP1 VDISP DP4/OR DP3/UR LATCH/HOLD Input to first clock inverter. Output of second clock inverter. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Backplane #3 output to display. Backplane #2 output to display. Backplane #1 output to display. Negative rail for display drivers. Input: When HI, turns on most significant decimal point. Output: Pulled HI when result count exceeds 19,999. Input: Second most significant decimal point on when HI. Output: Pulled HI when result count is less than 1000. Input: When floating, ADC operates in the Free Run mode. When pulled HI, the last displayed reading is held. When pulled LO, the result counter contents are shown incrementing during the de-integrate phase of cycle. Output: Negative going edge occurs when the data latches are updated. Can be used for converter status signal. Negative power supply terminal. Positive power supply terminal and positive rail for display drivers. Input to integrator amplifier. Output of integrator amplifier. Input: When LO, continuity flag on the display is OFF. When HI, continuity flag is ON. Output: HI when voltage between inputs is less than +200mV. LO when voltage between inputs is more than +200mV. Sets Common mode voltage of 3.2V below V+ for DE, 10X, etc. Can be used as pre-regulator for external reference. Positive side of external reference capacitor. Negative side of external reference capacitor. Output of buffer amplifier. Negative input voltage terminal. Positive input voltage terminal. Positive reference voltage. Negative reference voltage Function
Pin No. Pin No. Pin No. 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25
ANNUNCIATOR Backplane square wave output for driving annunciators.
B2, C 2, LO BATT Output to display segments.
23 24 25 26 27
20 21 22 23 24
26 27 28 29 30
VV+ INT IN INT OUT CONTINUITY
28 29 30 31 32 33 34 35
25 26 27 29 30 31 32 33
31 32 33 35 36 37 38 39
COMMON CREF + CREFBUFFER IN LO IN HI REF HI REF LO
2002 Microchip Technology Inc.
DS21459B-page 5
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TC7129
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Symbol DGND RANGE DP2 DP1 OSC2 NC Function Internal ground reference for digital section. See Section 4.3, 5V Power Supply. 3A pull-down for 200mV scale. Pulled HI externally for 2V scale. Internal 3A pull-down. When HI, decimal point 2 will be on. Internal 3A pull-down. When HI, decimal point 1 will be on. Output of first clock inverter. Input of second clock inverter. No connection. Pin No. Pin No. Pin No. 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC 36 37 38 39 40 -- 34 35 36 37 38 6,17, 28, 39 40 41 42 43 44 12, 23, 34, 1
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DS21459B-page 6
2002 Microchip Technology Inc.
TC7129
3.0 DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin PDIP.) The TC7129 is designed to be the heart of a high resolution analog measurement instrument. The only additional components required are a few passive elements: a voltage reference, an LCD, and a power source. Most component values are not critical; substitutes can be chosen based on the information given below. The basic circuit for a digital multimeter application is shown in Figure 3-1. See Section 4.0, Typical Applications for variations. Typical values for each component are shown. The sections below give component selection criteria. The resistor and capacitor values are not critical; those shown work for most applications. In some situations, the capacitor values may have to be adjusted to compensate for parasitic capacitance in the circuit. The capacitors can be low cost ceramic devices. Some applications can use a simple RC network instead of a crystal oscillator. The RC oscillator has more potential for jitter, especially in the least significant digit. See Section 4.8, RC Oscillator.
3.2
Integrating Resistor (RINT)
3.1
Oscillator (XOSC, CO1, CO2, R O)
The integrating resistor sets the charging current for the integrating capacitor. Choose a value that provides a current between 5A and 20A at 2V, the maximum full scale input. The typical value chosen gives a charging current of 13.3A:
The primary criterion for selecting the crystal oscillator is to choose a frequency that achieves maximum rejection of line frequency noise. To do this, the integration phase should last an integral number of line cycles. The integration phase of the TC7129 is 10,000 clock cycles on the 200mV range and 1000 clock cycles on the 2V range. One clock cycle is equal to two oscillator cycles. For 60Hz rejection, the oscillator frequency should be chosen so that the period of one line cycle equals the integration time for the 2V range:
EQUATION 3-2:
ICHARGE = 2V 13.3A 150k
Too high a value for RINT increases the sensitivity to noise pickup and increases errors due to leakage current. Too low a value degrades the linearity of the integration, leading to inaccurate readings.
EQUATION 3-1:
1/60 second = 16.7msec = 1000 clock cycles *2 OSC cycles/clock cycle OSC Frequency This equation gives an oscillator frequency of 120kHz. A similar calculation gives an optimum frequency of 100kHz for 50Hz rejection.
2002 Microchip Technology Inc.
DS21459B-page 7
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TC7129
FIGURE 3-1: STANDARD CIRCUIT
Low Battery Continuity V+ 5pF CO1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DP4 /OR
21
VDISP CONTINUITY INT OUT INT IN V+
22 23 24 25 26 27
ANNUNC
OSC3
OSC1
Display Drive Outputs
TC7129
COMMON REF LO RANGE REF HI CREF+ DGND CREFBUFF IN LO IN HI
120 kHz
OSC2 DP1
Crystal
VLATCH/ HOLD DP3 /UR
DP2
28
29
30
31
32
33
34
35
36
37
38
39
40
330k CINT 0.1F CREF+ 1F 150k RINT +
9V
RO 10pF 0.1 F CIF RREF 20 k DREF CRF 0.1F
CO2
V+
10k RBIAS - VIN
RIF 100k +
3.3
Integrating Capacitor (C INT)
The charge stored in the integrating capacitor during the integrate phase is directly proportional to the input voltage. The primary selection criterion for C INT is to choose a value that gives the highest voltage swing while remaining within the high linearity portion of the integrator output range. An integrator swing of 2V is the recommended value. The capacitor value can be calculated using the following equation:
The capacitor should have low dielectric absorption to ensure good integration linearity. Polypropylene and Teflon capacitors are usually suitable. A good measurement of the dielectric absorption is to connect the reference capacitor across the inputs by connecting: Pin to Pin: 20 33 (CREF+ to IN HI) 30 32 (CREF- to IN LO) A reading between 10,000 and 9998 is acceptable; anything lower indicates unacceptably high dielectric absorption.
EQUATION 3-3:
CINT = tINT x IINT VSWING
3.4
Reference Capacitor (CREF)
Where t INT is the integration time. Using the values derived above (assuming 60Hz operation), the equation becomes:
EQUATION 3-4:
CINT = 16.7msec x 13.3A = 0.1A 2V
The reference capacitor stores the reference voltage during several phases of the measurement cycle. Low leakage is the primary selection criterion for this component. The value must be high enough to offset the effect of stray capacitance at the capacitor terminals. A value of at least 1F is recommended.
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DS21459B-page 8
2002 Microchip Technology Inc.
TC7129
3.5 Voltage Reference (DREF, RREF, RBIAS, CRF)
FIGURE 4-1: POWERING THE TC7129 FROM A 5V POWER SUPPLY
The reference potentiometer (R REF) provides an adjustment for adjusting the reference voltage; any value above 20k is adequate. The bias resistor (RBIAS) limits the current through D REF to less than 150A. The reference filter capacitor (CRF) forms an RC filter with RBIAS to help eliminate noise.
+5V
TC7129
24 V+ 0.1F REF HI 34
3.6
Input Filter (RIF, CIF)
For added stability, an RC input noise filter is usually included in the circuit. The input filter resistor value should not exceed 100k. A typical RC time constant value is 16.7msec to help reject line frequency noise. The input filter capacitor should have low leakage for a high-impedance input.
35 REF LO 36 DGND 28 COMMON 0.1F 33 IN HI 0.1F IN LO V23 32 VIN
+ -
3.7
Battery
The typical circuit uses a 9V battery as a power source. Any value between 6V and 12V can be used. For operation from batteries with voltages lower than 6V and for operation from power supplies, see Section 4.2, Powering the TC7129.
-5V
4.4
Low Voltage Battery Source
4.0
4.1
TYPICAL APPLICATIONS
TC7129 as a Replacement Part
The TC7129 is a direct pin-for-pin replacement part for the ICL7129. Note, however, that part requires a capacitor and resistor between Pins 26 and 28 for phase compensation. Since the TC7129 uses internal phase compensation, these parts are not required and, in fact, must be removed from the circuit for stable operation.
A battery with voltage between 3.8V and 6V can be used to power the TC7129, when used with a voltage doubler circuit, as shown in Figure 4-2. The voltage doubler uses the TC7660 DC-to-DC voltage converter and two external capacitors.
FIGURE 4-2:
POWERING THE TC7129 FROM A LOW VOLTAGE BATTERY
24
4.2
Powering the TC7129
36
V+ REF HI
34
While the most common power source for the TC7129 is a 9V battery, there are other possibilities. Some of the more common ones are explained below.
+
3.8V to 6V
DGND REF LO COMMON 35 28 33 32
4.3
5V Power Supply
8 2
TC7129
IN HI IN LO V-
+
VIN
Measurements are made with respect to power supply ground. DGND (Pin 36) is set internally to about 5V less than V+ (Pin 24); it is not intended as a power supply input and must not be tied directly to power supply ground. It can be used as a reference for external logic, as explained in Section 4.6, Connecting to External Logic (see Figure 4-1).
-
+
TC7660
10F 4 5 3 10F
23
+
2002 Microchip Technology Inc.
DS21459B-page 9
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TC7129
4.5 +5V Power Supply
FIGURE 4-4:
Measurements are made with respect to power supply ground. COMMON (Pin 28) is connected to REF LO (Pin 35). A voltage doubler is needed, since the supply voltage is less than the 6V minimum needed by the TC7129. DGND (Pin 36) must be isolated from power supply ground (see Figure 4-3).
EXTERNAL LOGIC REFERENCED DIRECTLY TO DGND
V +
24
FIGURE 4-3:
POWERING THE TC7129 FROM A +5V POWER SUPPLY
External Logic 36 ILOGIC
TC7129
DGND
+5V
24 V+ 0.1F 34
23 V35
TC7129
36 0.1F 33 8 V+ 32 2 VDGND 28
FIGURE 4-5:
+
VIN
EXTERNAL LOGIC REFERENCED TO DGND WITH BUFFER
V+
-
+
23 10F
TC7660
GND 3
4 5 10F
24 External Logic
+
TC7129
-
4.6
Connecting to External Logic
ILOGIC
+
36
DGND 23
External logic can be directly referenced to DGND (Pin 36), provided that the supply current of the external logic does not exceed the sink current of DGND (Figure 4-4). A safe value for DGND sink current is 1.2mA. If the sink current is expected to exceed this value, a buffer is recommended (see Figure 4-5).
V-
4.7
Temperature Compensation
For most applications, VDISP (Pin 19) can be connected directly to DGND (Pin 36). For applications with a wide temperature range, some LCDs require that the drive levels vary with temperature to maintain good viewing angle and display contrast. Figure 4-6 shows two circuits that can be adjusted to give temperature compensation of about 10mV/C between V+ (Pin 24) and VDISP. The diode between DGND and VDISP should have a low turn-on voltage because VDISP cannot exceed 0.3V below DGND.
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DS21459B-page 10
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TC7129
FIGURE 4-6: TEMPERATURE COMPENSATING CIRCUITS
V+ V+
1N4148
39k 200k
24
39k 24 20k 2N2222 19 36 18k
TC7129
- 75k 23 19 36 VDISP DGND
TC7129
VDISP DGND 23
4.8
RC Oscillator
For applications in which 3-1/2 digit (100V) resolution is sufficient, an RC oscillator is adequate. A recommended value for the capacitor is 51pF. Other values can be used as long as they are sufficiently larger than the circuit parasitic capacitance. The resistor value is calculated as:
EQUATION 4-1:
R= 0.45 Freq * C
For 120kHz frequency and C = 51pF, the calculated value of R is 75k. The RC oscillator and the crystal oscillator circuits are shown in Figure 4-7.
FIGURE 4-7:
OSCILLATOR CIRCUITS
1 5pF V+
40 270k 10pF V+
120kHz
1
40 75k 51pF
2002 Microchip Technology Inc.
+
2 2
5k
V-
V-
4.9
Measuring Techniques
Two important techniques are used in the TC7129: successive integration and digital auto-zeroing. Successive integration is a refinement to the traditional dual slope conversion technique.
4.10
Dual Slope Conversion
A dual slope conversion has two basic phases: integrate and de-integrate. During the integrate phase, the input signal is integrated for a fixed period of time; the integrated voltage level is thus proportional to the input voltage. During the de-integrate phase, the integrated voltage is ramped down at a fixed slope, and a counter counts the clock cycles until the integrator voltage crosses zero. The count is a measurement of the time to ramp the integrated voltage to zero, and is, therefore, proportional to the input voltage being measured. This count can then be scaled and displayed as a measurement of the input voltage. Figure 4-8 shows the phases of the dual slope conversion.
TC7129
FIGURE 4-8:
Integrate
DUAL SLOPE CONVERSION
De-integrate
Zero Crossing
TC7129
Time
The dual slope method has a fundamental limitation. The count can only stop on a clock cycle, so that measurement accuracy is limited to the clock frequency. In addition, a delay in the zero crossing comparator can add to the inaccuracy. Figure 4-9 shows these errors in an actual measurement.
DS21459B-page 11
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TC7129
FIGURE 4-9: ACCURACY ERRORS IN DUAL SLOPE CONVERSION
Integrate
De-integrate
Over shoot due to zero crossing between clock pulses
Time
Integrator Residue Voltage
Over shoot caused by comparator delay of 1 clock pulse Clock Pulses
FIGURE 4-10:
Zero Integrate and Latch
INTEGRATION WAVEFORM
INT1 Integrate DE1 De-integrate
REST X10
DE2
REST
X10
DE3
Zero Integrate
TC7129
Integrator Note: Shaded area greatly expanded in time and amplitude.
Residual Voltage
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DS21459B-page 12
2002 Microchip Technology Inc.
TC7129
4.11 Successive Integration 4.12 Digital Auto-Zeroing
The successive integration technique picks up where dual slope conversion ends. The over shoot voltage shown in Figure 4-9, called the "integrator residue voltage," is measured to obtain a correction to the initial count. Figure 4-10 shows the cycles in a successive integration measurement. The waveform shown is for a negative input signal. The sequence of events during the measurement cycle is shown in Table 4-1. To eliminate the effect of amplifier offset errors, the TC7129 uses a digital auto-zeroing technique. After the input voltage is measured as described above, the measurement is repeated with the inputs shorted internally. The reading with inputs shorted is a measurement of the internal errors and is subtracted from the previous reading to obtain a corrected measurement. Digital auto-zeroing eliminates the need for an external auto-zeroing capacitor used in other ADCs.
TABLE 4-1:
MEASUREMENT CYCLE SEQUENCE
Description
4.13
Inside the TC7129
Figure 4-11 shows a simplified block diagram of the TC7129.
Phase INT1 DE1
Input signal is integrated for fixed time (1000 clock cycles on 2V scale, 10,000 on 200 mV). Integrator voltage is ramped to zero. Counter counts up until zero crossing to produce reading accurate to 3-1/2 digits. Residue represents an over shoot of the actual input voltage. Residue voltage is amplified 10 times and inverted. Integrator voltage is ramped to zero. Counter counts down until zero crossing to correct reading to 4-1/2 digits. Residue represents an under shoot of the actual input voltage. Residue voltage is amplified 10 times and inverted. Integrator voltage is ramped to zero. Counter counts up until zero crossing to correct reading to 5-1/2 digits. Residue is discarded.
REST Rest; circuit settles. X10 DE2
REST Rest; circuit settles. X10 DE3
2002 Microchip Technology Inc.
DS21459B-page 13
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TC7129
FIGURE 4-11: TC7129 FUNCTIONAL BLOCK DIAGRAM
Low Battery Continuity
Segment Drives
Backplane Drives Annunciator Drive
TC7129
OSC1 Latch, Decode Display Multiplexer OSC2
VDISP
Up/Down Results Counter OSC3 Sequence Counter/Decoder
Control Logic
RANGE L/H CONT V+ VDGND
DP1 DP2 UR/DP3 OR/DP4 Analog Section REF HI REF LO
INT OUT INT IN
COMMON
IN IN HI LO
BUFF
FIGURE 4-12:
INTEGRATOR BLOCK DIAGRAM
CREF REF HI REF LO RINT CINT
DE INT1 IN HI DE-
DE - + DE+ Buffer Integrator - + 100pF - Comparator 2 10 pF X10 Comparator 1 + To Digital Section
Common INT1, INT2 IN LO
DE+
DEINT REST
ZI, X10
- - Continuity V 200mV + +
500k Continuity Comparator
TC7129
To Display Driver
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DS21459B-page 14
2002 Microchip Technology Inc.
TC7129
4.14 Integrator Section
FIGURE 4-13:
The integrator section includes the integrator, comparator, input buffer amplifier, and analog switches (see Table 4-2), used to change the circuit configuration during the separate measurement phases described earlier. See Integrator Block Diagram (Figure 4-12).
IN HI
CONTINUITY INDICATOR CIRCUIT
- + Buffer
TABLE 4-2:
Label Label DE DE- DE+ INT1 INT2 INT REST ZI X10 X10
SWITCH LEGENDS
Description
COM
Meaning. Open during all de-integrate phases. Closed during all de-integrate phases when input voltage is negative. Closed during all de-integrate phases when input voltage is positive. Closed during the first integrate phase (measurement of the input voltage). Closed during the second integrate phase (measurement of the amplifier offset). Open during both integrate phases. Closed during the rest phase. Closed during the zero integrate phase. Closed during the X10 phase. Open during the X10 phase.
CONT IN LO - 200mV V + 500k To Display Driver (Not Latched)
TC7129
FIGURE 4-14:
INPUT/OUTPUT PIN SCHEMATIC
TC7129
The buffer amplifier has a Common mode input voltage range from 1.5V above V- to 1V below V+. The integrator amplifier can swing to within 0.3V of the rails, although for best linearity, the swing is usually limited to within 1V. Both amplifiers can supply up to 80A of output current, but should be limited to 20A for good linearity.
DP4/OR, Pin 20 DP3/UR, Pin 21 LATCH/HOLD Pin 22 CONTINUITY, Pin 27
500k
4.15
Continuity Indicator 4.16 Common and Digital Ground
A comparator with a 200mV threshold is connected between IN HI (Pin 33) and IN LO (Pin 32). Whenever the voltage between inputs is less than 200mV, the CONTINUITY output (Pin 27) will be pulled HIGH, activating the continuity annunciator on the display. The continuity pin can also be used as an input to drive the continuity annunciator directly from an external source (see Figure 4-13). A schematic of the input/output nature of this pin is also shown in Figure 4-14.
The common and digital ground (DGND) outputs are generated from internal zener diodes. The voltage between V+ and DGND is the internal supply voltage for the digital section of the TC7129. Common can source approximately 12A; DGND has essentially no source capability (see Figure 4-15).
2002 Microchip Technology Inc.
DS21459B-page 15
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TC7129
FIGURE 4-15: DIGITAL GROUND (DGND) AND COMMON OUTPUTS
24 12A 3.2V 28 - N + Logic Section 36 5V COM V+
4.20
LATCH/Hold
The L/H output goes LOW during the last 100 cycles of each conversion. This pulse latches the conversion data into the display driver section of the TC7129. This pin can also be used as an input. When driven HIGH, the display will not be updated; the previous reading is displayed. When driven LOW, the display reading is not latched; the sequence counter reading will be displayed. Since the counter is counting much faster than the backplanes are being updated, the reading shown in this mode is somewhat erratic.
TC7129
N
P
DGND
4.21
Display Driver
23
V-
4.17
Low Battery
The low battery annunciator turns on when supply voltage between V- and V+ drops below 6.8V. The internal zener has a threshold of 6.3V. When the supply voltage drops below 6.8V, the transistor tied to V- turns OFF, pulling the "Low Battery" point HIGH.
The TC7129 drives a triplexed LCD with three backplanes. The LCD can include decimal points, polarity sign, and annunciators for continuity and low battery. Figure 4-16 shows the assignment of the display segments to the backplanes and segment drive lines. The backplane drive frequency is obtained by dividing the oscillator frequency by 1200. This results in a backplane drive frequency of 100Hz for 60Hz operation (120kHz crystal) and 83.3Hz for 50Hz operation (100kHz crystal). Backplane waveforms are shown in Figure 4-17. These appear on outputs BP1, BP2, BP3 (Pins 16, 17, and 18). They remain the same, regardless of the segments being driven. Other display output lines (Pins 4 through 15) have waveforms that vary depending on the displayed values. Figure 4-18 shows a set of waveforms for the A, G, D outputs (Pins 5, 8, 11, and 14) for several combinations of "ON" segments. The ANNUNCIATOR DRIVE output (Pin 3) is a square wave, running at the backplane frequency (100Hz or 83.3Hz) with a peak-to-peak voltage equal to DGND voltage. Connecting an annunciator to Pin 3 turns it ON; connecting it to its backplane turns it OFF.
4.18
Sequence and Results Counter
A sequence counter and associated control logic provide signals that operate the analog switches in the integrator section. The comparator output from the integrator gates the results counter. The results counter is a six-section up/down decade counter, which holds the intermediate results from each successive integration.
4.19
Over Range and Under Range Outputs
When the results counter holds a value greater than 19,999, the DP4/OR output (Pin 20) is driven HIGH. When the results counter value is less than 1000, the DP3/UR output (Pin 21) is driven HIGH. Both signals are valid on the falling edge of LATCH/HOLD (L/H) and do not change until the end of the next conversion cycle. The signals are updated at the end of each conversion, unless the L/H input (Pin 22) is held HIGH. Pins 20 and 21 can also be used as inputs for external control of decimal points 3 and 4. Figure 4-14 shows a schematic of the input/output nature of these pins.
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DS21459B-page 16
2002 Microchip Technology Inc.
TC7129
FIGURE 4-16: DISPLAY SEGMENT ASSIGNMENTS
Low Battery Continuity
BP1 BP2 Backplane Connections
BP3 Low Battery Continuity
F4, E4, DP4 A4, G4, D4 B4, C4, BC4 F3, E3, DP3 A3, G3, D3 B3, C3, MINUS
B1, C1, Continuity A1, G1, D1 F1, E1, DP1 B2, C2, Low Battery A2, G2, D2 F2, E2, DP2
FIGURE 4-17:
BACKPLANE WAVEFORMS
FIGURE 4-18:
TYPICAL DISPLAY OUTPUT WAVEFORMS
VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP VDD VH
BP1
b Segment Line All Off
BP2
a Segment On d, g Off
BP3
a, g On d Off
All On VL VDISP
2002 Microchip Technology Inc.
DS21459B-page 17
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TC7129
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available a this time.
5.2
Taping Forms
Component Taping Orientation for 44-Pin PLCC Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PLCC
32 mm
24 mm
500
13 in
Note: Drawing does not represent total number of pins.
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P Standard Reel Component Orientation for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
44-Pin PQFP
24 mm
16 mm
500
13 in
Note: Drawing does not represent total number of pins.
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DS21459B-page 18
2002 Microchip Technology Inc.
TC7129
5.3 Package Dimensions
40-Pin PDIP (Wide)
PIN 1
.555 (14.10) .530 (13.46)
2.065 (52.45) 2.027 (51.49)
.610 (15.49) .590 (14.99)
.200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) 3 MIN.
.110 (2.79) .090 (2.29)
.070 (1.78) .045 (1.14)
Dimensions: inches (mm)
44-Pin PLCC
PIN 1
.050 (1.27) TYP. .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51)
.021 (0.53) .013 (0.33) .630 (16.00) .591 (15.00) .032 (0.81) .026 (0.66)
.656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .180 (4.57) .165 (4.19)
.020 (0.51) MIN. .120 (3.05) .090 (2.29)
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21459B-page 19
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TC7129
5.3 Package Dimensions (Continued)
44-Pin PQFP
.009 (0.23) .005 (0.13)
7 MAX.
PIN 1 .018 (0.45) .012 (0.30)
.041 (1.03) .026 (0.65)
.398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65)
.031 (0.80) TYP.
.398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65)
.010 (0.25) TYP. .083 (2.10) .075 (1.90) .096 (2.45) MAX.
Dimensions: inches (mm)
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DS21459B-page 20
2002 Microchip Technology Inc.
TC7129
NOTES:
2002 Microchip Technology Inc.
DS21459B-page 21
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TC7129
SALES AND SUPPORT
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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DS21459B-page 22
2002 Microchip Technology Inc.
TC7129
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21459B-page 23
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WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
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China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
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Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599
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Chicago
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EUROPE
Denmark
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India
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03/01/02
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DS21459B-page 24
2002 Microchip Technology Inc.
*B95412SD*


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